Saifun Semiconductors Ltd. has developed a conventional, exemplary involatile memory consisting of 2-bit field-effect transistors. See, among others, published Japanese translation of PCT publication 2001-512290 (Tokuhyo 2001-512290; published on Jun. 8, 2001), an equivalent to WO99/07000 published on 11 Feb. 1999. The structure of this conventional art memory will be discussed below.
The memory, as shown in FIG. 21, includes (i) a gate electrode 909 formed above a p-type well region 901 with an intervening gate insulating film and (ii) a first n-type diffusion layer region (n-impurities diffusion region) 902 and a second n-type diffusion layer region 903 formed on the surface of the p-type well region 901. The gate insulating film is made of “ONO” (Oxide Nitride Oxide) stacks where silicon oxide films 904, 905 sandwich a silicon nitride film 906. In the silicon nitride film 906, near the ends of the first n-type diffusion layer region 902 and the second n-type diffusion layer region 903 are there provided respectively a memory (charge) retentive section 907 and a memory (charge) retentive section 908.
The charge in these memory retentive sections 907, 908 is individually read out in the form of the transistor's drain current so that a single transistor can store 2 bits of information.
However, in the memory, the gate insulating film is difficult to make thinner, because the gate insulating film has a three-layer, or ONO, structure so that the film will give functionality to the transistor and behave by itself as a memory film storing electric charge. Further, at shorter channel lengths, the memory retentive sections 907, 908 in each transistor have difficulty in the 2 bit operation due to increasing interference with each other. These factors have been obstructing further miniaturization of the device.